1. Field of the Invention
The present invention relates to gain-controlled amplifiers, and more specifically to a dual mode gain-controlled amplifier.
2. Description of the Related Art
A prior art variable gain amplifier, as shown in FIG. 1, comprises transistors 101 to 105. When a bias voltage VB is higher than a bias voltage VA and the transistor 105 is non-conducting, the other transistors operate as a cascode amplifier. As a result, the variable gain amplifier operates in a high gain mode. When the voltage VB is lower than the voltage VA, the transistor 105 is conducting and the transistor 101 operates as an amplifier. The signal amplified by transistor 101 is bypassed through a Vcc line (AC ground) and the variable gain amplifier operates in a low gain mode. Usually, when the signal at the input terminal 108 is high, the prior art variable gain amplifier is set in the low gain mode to prevent distortion. However, if the input signal is higher than a designed critical value of the low gain mode, the high input voltage will cause transistors 101 and 102 to produce distorted collector currents. Although part of the distorted collector currents is bypassed through the AC grounded circuit, the remaining current will cause a distorted voltage to appear at the output terminal 109.
According to Japanese Patent Publication 2000-278061, a prior art variable gain amplifier comprises a cascode amplifier, first to fourth transistors, an emitter resistance and a bias switching circuit. The cascode amplifier is connected to the collector of the emitter-grounded first transistor and to the emitter of the second transistor whose base is RF-coupled to ground through a first ground capacitance. The third transistor has its base RF-coupled to ground through a second ground capacitance, has its emitter connected to the base of the first transistor and has its collector connected to the collector of the second transistor. The fourth transistor, connected to the emitter of the third transistor, operates as a constant current source. The emitter resistance is used to connect the emitter of the fourth transistor to ground. The bias switching circuit is used to supply bias voltage to the base of each of the first to fourth transistors. By using the turn-off condition of the first transistor and the bias switching circuit, the cascode amplifier is operated for high gain operation and the third transistor is used for low gain operation.
Japanese Patent Publication 2000-101371 discloses another variable gain amplifier which is a cascode amplifier in which the collectors of emitter-grounded first and second transistors are connected to the emitter of a third transistor whose base is RF-coupled to ground. The variable gain amplifier is further provided with a feedback resistance, a bias switching circuit, a first impedance compensating circuit and a second impedance compensating circuit. Via the feedback resistance, the emitter of the second transistor is connected to ground. The bias switching circuit selects one of the first and second transistors for supplying a bias voltage. The first impedance compensating circuit controls the input of the second transistor and the second impedance compensating circuit is connected tot he base of each of the first and second transistors.
Japanese Patent Publication 1999-68471 discloses a transistor amplifier comprising an emitter-grounded input transistor and a pre-distortion circuit connected to the base of the input transistor. The pre-distortion circuit includes a base-emitter coupling and a semiconductor coupling whose direction of current is opposite to that the base-emitter coupling.
Therefore, there exists a need to provide a low-noise gain-controlled amplifier for producing a low-noise, high-gain output signal when one of the input and output signals is low and a low-distortion, low-gain output signal when one of such signals is high.
It is therefore an object of the present invention to provide a low-noise gain-controlled amplifier capable of producing a low-noise, high-gain output signal when the amplifier is set in a high gain mode, and a low-distortion, low-gain output signal when the amplifier is set in a low gain mode.
According to a first aspect of the present invention, there is provided a gain-controlled amplifier comprising an input terminal for receiving an input signal, an output terminal for delivering an output signal, first, second and third transistors, and control circuitry. The control circuitry compares one of the input and output signals with a predetermined value and causing the second and third transistors to be respectively turned into conducting and non-conducting states when the compared signal is lower than the predetermined value, and respectively turned into non-conducting and conducting states when the compared signal is higher than the predetermined value. When the third transistor is turned into the non-conducting state, the first and second transistors are configured to form a cascode amplifier between the input and output terminals. When the second transistor is turned into the non-conducting state, the first and third transistors being configured so that the third transistor forms a base-grounded amplifier between the input and output terminals and the first transistor forms a diode for supplying a DC bias current to the third transistor.
According to a second aspect of the present invention, there is provided a gain-controlled amplifier comprising first and second input terminals, second input and output terminals, first to sixth transistors. The second and fifth transistors are connected together to form a first transistor pair, and the third and sixth transistors are connected together to form a second transistor pair. Control circuitry is provided for comparing a signal at one of the first input and first output terminals with a predetermined value and comparing a signal at one of the second input and second output terminals with the predetermined value. The control circuitry causes the first and second transistor pairs to be respectively turned into conducting and non-conducting states when at least one of the compared signals is lower than the predetermined value and respectively turned into non-conducting and conducting states when both of the compared signals are higher than the predetermined value. When the second transistor pair is turned into the non-conducting state, the first and second transistors are configured to form a first cascode amplifier between the first input and output terminals and the fourth and fifth transistors are configured to form a second cascode amplifier between the second input and output terminals. When the first transistor pair is turned into the non-conducting state, the first and third transistors are configured so that the third transistor forms a first base-grounded amplifier between the first input and output terminals and the first transistor forms a first diode for supplying a DC bias current to the third transistor. Simultaneously, the fourth and sixth transistors are configured so that the sixth transistor forms a second base-grounded amplifier between the second input and output terminals and the fourth transistor forms a second diode for supplying a DC bias current to the sixth transistor.